Testablility method for embedded core - based integrated circuits 嵌入式基于芯片的集成電路的可試性方法
Standard testability method for embedded core - based integrated circuits c tt 嵌入式基于芯片的集成電路c tt的標(biāo)準(zhǔn)可試性方法
In this paper , we investigate the problem of soc test and introduce embedded core test international standard ieee p1500 本文對(duì)soc的測(cè)試問(wèn)題進(jìn)行了初步研究,并介紹了嵌入式核測(cè)試標(biāo)準(zhǔn)ieeep1500 。
The result shows that forming a high capability ac control ic using this ip as an embedded core with other cpu or dsp core can efficiently shorten the cpu processing time and constitute high performance close - loop control system . some of the ips about the communication between d / a convert , i2c devices and control ics are also created 這種速度估算ip核作為一種通用的片內(nèi)外設(shè)形式(以硬件形式完成軟件功能) ,和裸mcu (或dsp )核制成電機(jī)控制專(zhuān)用芯片,可應(yīng)用于各種無(wú)速度傳感器的電機(jī)控制場(chǎng)合。